It is a common practice to integrate memory and logic functions on a common semiconductor substrate. In such a configuration, when the memory function is performed by a dynamic random access memory (DRAM) cell, the circuitry is referred to as embedded DRAM (eDRAM).
The use of eDRAM as microprocessor cache, however, involves making tradeoffs between performance parameters, such as speed, retention time and power consumption, and production parameters, such as yield and design complexity. Due to their small sizes, memory cells are especially susceptible to process-induced variations, which worsen these tradeoffs and compromise memory cell functionality. Thus, steps need to be taken to minimize process-induced variations.
The use of undoped channel devices such as fin-field effect transistors (FinFETs) for memory (both static random access memory (SRAM) and DRAM) has been proposed for this reason. However, the integration of FinFETs with planar logic is difficult due to vertical topography, especially since DRAM processes generally rely on bulk silicon wafer substrates. Various problems in extrapolating planar DRAM technology to FinFETs lie in the fact that there is no unprocessed side to the body of the transistor where the capacitor can be strapped to. Also, the thin body of the Fin allows for very little overlap area for intimate electrical contact. The tight overlap requirements for deep trench to fin alignment is exacerbated by the planarity requirements of a Side wall Image Transfer (SIT) process required to obtain sub-lithographic Fin pitches. As such, conventional techniques are unable to use FinFETs for eDRAM.